< 2024 >

• Dongwon Jo, Taesu Kim, Yulhwa Kim*, Jae-Joon Kim*, "Mixture of Scales: Memory-Efficient Token-Adaptive Binarization for Large Language Models," Conference on Neural Information Processing Systems (NeurIPS), Dec. 2024 (*co-corresponding author) (Accepted) 

• Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim*, Jae-Joon Kim*, "SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks," International Conference on Machine Learning (ICML), Jul. 2024. (*co-corresponding author)

• Hyesung Jeon, Yulhwa Kim*, and Jae-Joon Kim*, "L4Q: Parameter Efficient Quantization-Aware Fine-Tuning on Large Language Models," arXiv preprint arXiv:2402.04902, Feb. 2024. (*co-corresponding author)

• Jaeyong Jang*, Yulhwa Kim*, Juheun Lee, Jae-Joon Kim, "FIGNA: Integer Unit-based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Mar. 2024. (*equally contributed)

< 2023 >

• Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Taesu Kim, Daehyun Ahn, Hyungjun Kim, Jae-Joon Kim, "Leveraging Early-Stage Robustness in Diffusion Models for Efficient and High-Quality Image Synthesis," Conference on Neural Information Processing Systems (NeurIPS), Dec. 2023

• Jiwoong Choi, Minkyu Kim, Daehyun Ahn, Taesu Kim. Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Jae-Joon kim, Hyungjun Kim, "Squeezing Large-Scaling Diffusion Models for Mobile," ICML 2023 Workshop on Challenges of Deploying Generative AI, Jul. 2023

• Yulhwa Kim, Jaeyong Jang, Jehun Lee, Jihoon Park, Jeonghoon Kim, Byeongwook Kim, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Jae-Joon kim, "Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic," International Conference on Learning Representations (ICLR), May. 2023.

< ~ 2022 >

• Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim, "Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, no. 4, pp. 1-19, Oct. 2022.

• Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim, "Energy-Efficient In-Memory Binary Neural Network Accelerator Design based on 8T2C SRAM Cell," IEEE Solid-State Circuits Letter (SSC-L), vol. 5, pp. 70-73, Mar. 2022.

• Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim, "BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 6, pp. 1924-1935, Jun. 2022.

• Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim, "Energy-Efficient Charge sharing-Based 8T2C SRAM in-Memory Accelerator for Binary Neural Networks in 28nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.

• Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim, Jihoon Park and Jae-Joon Kim, "Single RRAM Cell-Based In-Memory Accelerator Architecture for Binary Neural Networks," IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS), Jun. 2021.

• Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim, "Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs," Design, Automation and Test in Europe Conference and Exhibition (DATE), Feb. 2021.

• Daehyun Ahn, Hyunmyung Oh, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim, "Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators," IEEE Access, vol. 9, pp. 141961-141969, Oct. 2021.

• Wangxin He, Shihui Yin, Yulhwa Kim, Xiaoyu Sun, Jae-Joon Kim, Shimeng Yu, and Jae-sun Seo, "2-Bit-per-Cell RRAM based In-Memory Computing for Area-/Energy-Efficient Deep Learning," IEEE Solid-State Circuits Letter (SSC-L), vol. 3, pp. 194-197, Jul. 2020.

• Naebeom Park, Yulhwa Kim, Daehyun Ahn, Taesu Kim, Jae-Joon Kim, "Time-Step Interleaved Weight Reuse for LSTM Neural Network Computing," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2020.

• Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim, "Algorithm-Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead," ACM/IEEE Design Automation Conference (DAC), Jul. 2020.

• Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim, "A 44.1 TOPS/W Precision-Scalable Hardware Accelerator for Quantized Neural Networks in 28nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020.

• Shihui Yin, Yandong Luo, Yulhwa Kim, Wangxin He, Xu Han, Xiaoyu Sun, Hugh Barnaby, Jae-Joon Kim, Shimeng Yu, and Jae-sun Seo, "Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning," IEEE Micro, vol. 39, no. 6, pp. 54-63, Nov.-Dec. 2019.

• Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim, "Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array," Symposium on VLSI Circuits (VLSI Symp), Jun. 2019.

• Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim, "BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function," arXiv preprint arXiv:1903.09807, Mar. 2019.

• Wooseok Yi, Yulhwa Kim, Jae-Joon Kim, "Effect of Device Variation on mapping Binary Neural Network to Memristor Crossbar Array," Design Automation and Test in Europe (DATE), Mar. 2019.

• Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim, "In-Memory Batch-Normalization for Resistive Memory based Binary Neural Network Hardware," Asian South-Pacific Design Auotmation Conference (ASP-DAC), Jan. 2019.

• Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim, "Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators," arXiv preprint arXiv:1811.02187, Nov. 2018.

• Jinseok Kim, Yulhwa Kim, Sungho Kim, Jae-Joon Kim, "Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay," International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2018.

• Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim, "Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array," International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2018.